1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacture, and more particularly to a method for manufacturing an improved metal oxide semiconductor (MOS) transistor.
2. Description of the Prior Art
Field effect transistors (FETs) are the basic building block of today""s integrated circuit. Such transistors can be formed in conventional substrates (such as silicon) or in silicon-on-insulator (SOP) substrates.
State of the art MOS transistors are fabricated by depositing a gate stack material over a gate dielectric and a substrate. Generally, the MOS transistor fabrication process implements lithography and etching processes to define the conductive, e.g., poly-Si, Si, gate structures. The gate structure and substrate are thermally oxidized, and, after this, source/drain extensions are formed by implantation. Sometimes the implant is performed using a spacer to create a specific distance between the gate and the implanted junction. In some instances, such as in the manufacture of an NFET device, the source/drain extensions for the NFET device are implanted with no spacer. For a PFET device, the source/drain extensions are typically implanted with a spacer present. A thicker spacer is typically formed after the source/drain extensions have been implanted. The deep source/drain implants are then performed with the thick spacer present. High temperature anneals are performed to activate the junctions after which the source/drain and top portion of the gate are silicided. Silicide formation typically requires that a refractory metal be deposited on the silicon wafer followed by a high temperature thermal anneal process to produce the silicide material.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find a way to further downscale the dimensions of field effect transistors (FETs), such as metal oxide semiconductors. The downscaling of transistor dimensions allows for improved performance as well as compactness, but such downscaling has some device degrading effects. Generational improvements for high performance MOS devices are obtained by decreasing the transistor line width (L poly), reducing the gate oxide thickness, and decreasing the source/drain extension resistance. Smaller L poly results in less distance between source and drain. This results in faster switching speeds for complementary metal oxide semiconductor (CMOS) circuits. However, as the L poly gets smaller, the overall area available for silicidation is reduced. This means that as L poly shrinks, line resistance is increased. Increased line resistance causes degradation in device performance.
Drive currents for MOS devices are inversely proportional to gate dielectric thickness. Thinner gate oxides yield higher drive currents. One problem with this, however, is that as the gate oxide is thinned, poly depletion effects become more pronounced. Poly depletion is an effective thickening of the gate oxide. One prior art method to overcome this problem is gate predoping, In this prior art technique, the blanket poly-Si is implanted prior to gate patterning. The problem with the predoping method is that the gate profiles and etching are difficult to control.
Source/drain extension resistance is another important performance factor. Drive currents may be increased by reducing source/drain extension resistance. Increasing the source/drain extension dose leads to lower resistance but has an undesirable side effect of increasing the junction depth. One method for overcoming this problem is to implant the extension first with no spacer present and then form a thin spacer and perform a second implant. Alternatively, a notched gate may be used to perform this task by implanting at two or more angles. The drawback of the first method is increased process complexity; while the drawback of the second method is that notched gates typically have reduced line width control.
It would be highly desirable to provide a MOS transistor device that has sub-lithographic channel length, improved gate activation characteristics, reduced gate conductor line resistance, and reduced source/drain extension resistance.
It is an object of this invention to provide a high performance MOS transistor device having sub-lithographic channel length, improved gate activation characteristics, reduced gate conductor line resistance, and reduced source/drain extension resistance. The term xe2x80x9csub-lithographic channel lengthxe2x80x9d denotes a channel length that is about 0.7 F. or less, more preferably from about 0.5 F. or less, wherein F is the minimum feature size. Sub-lithographic dimensions are less than the minimum dimension that can be reliably produced utilizing conventional lithography and etching techniques.
According to a preferred embodiment of the present invention, there is provided a novel damascene gate process that satisfies the above requirements. In the improved process of the present invention, lower and upper portions of the gate conductor are independently defined. The width of the lower portion of the gate conductor defines the channel length of the MOSFET and is sub-lithographic minimum width for high performance. The upper portion is wider than the lower portion, and may be greater than lithographic minimum dimension. The silicided, or self-aligned silicide (salicide), wider upper portion provides for gate conductor resistance which is lower than what is obtainable from the presently known ark providing reduced delay and dispersion of pulses propagating down a long gate conductor. It is understood that the wider upper portion may alternatively include a metallic region.
Advantageously, besides defining sub-lithographic channel length defined by a lower gate conductor portion, there is a low gate resistance, for even higher performance, due to the wider upper gate conductor portion, which may comprise a silicide or comprise a metal. It is understood that the narrow lower and upper portions are self-aligned to each other. Further, the gate conductor may further be degeneratively doped, for minimization of gate depletion effects, without compromising S/D junction doping.
A high performance MOSFET providing the above elements and advantages is provided including a substrate; a sub-lithographic channel defined in the substrate by a narrow lower gate conductor portion; a wider upper gate conductor portion self-aligned with the narrow lower gate conductor portion; and source and drain diffusion regions formed on either side of the channel. The above described MOSFET device exhibits low gate line resistance and enhanced sub-lithographic channel length performance.
In broad terms, the inventive structure is prepared using a method which comprises:
a) providing a structure of one or more pad layers to function as a mandrel over a semiconductor substrate, said one or more pad layers having an aperture;
b) depositing a dielectric material within said aperture;
c) forming respective spacer elements on either sidewall of said aperture overlying said dielectric material in said aperture;
d)removing a portion of said dielectric material not underlying said spacer elements within said aperture to define a region of sub-lithographic width;
e) depositing a gate dielectric in said region, wherein said gate dielectric is positioned between a remaining portion of said dielectric material;
f) depositing a first gate conductor material in said region to form a sub-lithographic lower gate conducting portion within said aperture;
g) depositing a second gate conductor material to form an upper gate conducting portion within said aperture having a dimension that is wider than said sub-lithographic lower gate conducting portion, and self-aligned to said sub-lithographic lower gate conductor portion;
wherein a resulting MOSFET device includes a sub-lithographic channel length according to said sub-lithographic lower gate conducting portion.
More specifically, the above inventive structure may be produced using a method which includes at least the steps of: providing a pad dielectric layer to function as a mandrel layer over a semiconductor substrate; forming an aperture defining a gate region for a MOSFET device in the mandrel layer; depositing a dielectric material above the mandrel layer and in the aperture bordering the mandrel layer, forming respective spacer elements on either sidewall of the aperture overlying the dielectric material in the aperture; removing a portion of the dielectric material in the aperture not lying underneath the spacers to define a sub-lithographic image width, depositing a gate dielectric in the aperture at the sub-lithographic image width; forming a lower gate conducting portion between the remaining dielectric material in the aperture; removing the spacer elements; forming an upper gate conducting portion between the mandrel layer in an upper portion of the aperture, the upper portion being wider than the lower portion and self-aligned with said lower gate conducting portion; wherein the resulting MOSFET device includes a sub-lithographic channel defined by a narrow lower portion of a lower gate conducting portion and, exhibits the lower gate resistance due to the wider upper gate conducting portion.